The invention relates to a single-ended high-voltage level shifter for a TFT-LCD gate driver, and more particularly, to a single-ended high-voltage level shifter that minimizes the chip area of a TFT-LCD gate driver.
A functional block diagram of a typical TFT-LCD gate driver with 256 output channels for XGA/SXGA display systems is shown in FIG. 1. The gate driver includes a bidirection shift control register, an enable control, a level shifter and an output buffer. The bidirection shift control register, triggered synchronously by the rising edge of a shift clock (SCLK), is used to continuously shift the start pulses of the right data input/output (DIOR) or the left data input/output (DIOL) according to the right/left shift control signal (RL). Each output channel of the gate driver is gated asynchronously by the global-on control signal (XON) and the output-enabled signal (OE). Then the voltage level of each output channel of the gate driver is translated to drive the output buffer of the next stage.
A conventional implementation of the level shifter 21 and the output buffer 22 is shown in FIG. 2. The level shifter 21 includes two high-voltage PMOS transistors M1, M3 and two high-voltage NMOS transistors M2, M4. Herein, the high-voltage MOS transistor is different from the low-voltage MOS transistor in that the high-voltage MOS transistor withstands higher drain-to-source or gate-to-source voltage than that of the low-voltage MOS transistor, for example: 40V. The threshold voltage VT of the high-voltage MOS transistor is also higher than the low-voltage MOS transistor. For example, the threshold voltage of the high-voltage PMOS transistor is 1.7V, and the threshold voltage of the high-voltage NMOS transistor is 2.7V. The input signal IN is used to drive the transistor M2, and the complementary input signal INB is used to drive the transistor M4.
When the gate of the transistor M2 receives an input low signal VSS, the low-voltage power supply, for example: xe2x88x925V. The transistor M2 is OFF and the transistor M4 is ON. The voltage of node B is pulled to VSS, and the transistor M1 is ON. The voltage of node A is then pulled to the high-voltage power supply VDD, for example: 25Vxcx9c35V, then M3 is OFF. As a result, the transistor M6 is ON and the voltage of the output signal OUT is VSS. When the input signal IN applied at the gate of the transistor M2 is changed from low to high, for example: xe2x88x925V+3.3V=xe2x88x921.7V, the transistor M2 is ON, and the transistor M4 is OFF. The voltage of node A is pulled to VSS and the transistor M3 is ON. The voltage of node B is pulled to VDD. Then the transistor M1 is OFF. Because the voltage of node A is VSS, the transistor M5 is ON and the voltage of the output signal OUT is pulled to VDD.
The advantage of this conventional circuitry is that there is no static power consumption in the level shifter 21. However, the sizes of the high-voltage transistors M2 and M4 have to be designed much larger than those of the high-voltage transistors M1 and M3 as the high level of the input signal does not differ much from the threshold voltage of the high-voltage transistors M2 and M4. The reason is that when the high-voltage transistor M2 (or M4) is ON, the voltage of node A (or B) should be pulled from the high-voltage power supply VDD to the low-voltage power supply VSS in a short period of time. Thus the sizes of the high-voltage transistors M2 and M4 have to be designed large enough to sustain the large current. In addition, the high level of the input signal is necessarily higher than the threshold voltage of the high-voltage transistors M2 and M4 (typical of 2.7V) in order to drive the level shifter shown in FIG. 2.
FIG. 3 shows a circuit diagram having the level shifter 31 and the output buffer 32 connected together according to another prior art wherein the circuitry of the output buffer 32 is identical to that of the output buffer 22 shown in FIG. 2. The low-voltage transistors M7 and M8 receive the input signal IN and the complementary input signal INB respectively. The source of the high-voltage transistor M2 is connected to the drain of the low-voltage transistor M7 and the source of the high-voltage transistor M4 is connected to the drain of the low-voltage transistors M8. Both the gates of M2 and M4 are connected to a reference voltage VRL to limit the voltage of the drains of M7 and M8 not to exceed VRL-VT, for example: 5Vxe2x88x922.7V=2.3V. This is to prevent M7 (or M8) from breakdown when the voltage of drain-to-source of M7 (or M8) is excessively high. The advantage of this conventional circuitry is that the sizes of the high-voltage transistors M2 and M4 are not necessarily designed much larger than those of the high-voltage transistors M1 and M3 like the circuitry shown in FIG. 2. This is due to the employment of the low-voltage transistors M7 and M8. As a result, the chip area of the level shifter 31 is smaller than that of the level shifter 21.
Although the level shifter 31 occupies smaller chip area than the level shifter 21, the level shifter 31 still uses 4 high-voltage transistors that occupy significant chip area. Therefore, this plays an important role in determining the cost of the gate driver IC.
In view of the foregoing problems, the object of the invention is to provide a single-ended high-voltage level shifter for the TFT-LCD gate driver. Employing only two high-voltage transistors minimizes the chip area of the single-ended high-voltage level shifter. Implementing partial logic control circuitry in the level shifter further minifies the chip area of the TFT-LCD gate driver. Therefore, the total cost of the gate driver IC is significantly reduced.
The single-ended high-voltage level shifter for the TFT-LCD gate driver comprises (a) a high-voltage power supply and a low-voltage power supply; (b) a first low-voltage NMOS transistor, having its gate connected to an input signal and its source connected to the low-voltage power supply; (c) a high-voltage NMOS transistor, having its gate received a first reference voltage whose level is between the input-signal level and the high-voltage power supply, and having its source connected to the drain of the first low-voltage NMOS transistor; (d) a first high-voltage PMOS transistor, having its gate received a second reference voltage that keeps the first high-voltage PMOS transistor in ON-state and is at a level higher than the first reference voltage, and having its source connected to the high-voltage power supply, and having its drain connected to the drain of the high-voltage NMOS transistor and employed as the output end connected to an output driver of the next stage.